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wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 1 / 29 2.95 C 6v / 4 a / 0.8 C 3.6v output d escription the magi3c 171020302, 171040302 and 171060302 power module family provide a fully integrated dc - dc power supply including the switching regulator , regulation loop, power mosfets and shielded inductor in one package. this modules require as few as 3 external components the 1710 4 0302 offers high efficiency and delivers u p to 4 a of output current. it operates from 2.95 to 6v input voltage and is designed for fast transient response. it is available in a standard industrial high power density qfn package (11mm x 9mm x 2.8mm) with very good thermal performance . th is module h as an on - board protection circuitry to guard against thermal overstress and electrical damage featuring thermal shut - down, over - current, short - circuit, over - voltage and under - voltage protections. typical applications ? point - of - load dc - dc applications from 5v and 3.3v rails ? industrial, test & measurement, medical applications ? system power supplies ? dsps, fpgas, mcus and mpu supply ? i/o interface power supply ? communication infrastructure ? high density distributed power systems typical circuit diagram features ? peak efficiency up to 9 6 % ? current capability up to 4 a ? output voltage range: 0.8 to 3.6v ? current mode control ? synchron u os operation ? 1% reference accuracy over temperature ? adjustable switching frequency (0.5 to 2 mhz) ? continuous output power: 14 . 4 w ? no derating within the operating temperature range ? integrated shielded inductor ? under - voltage lockout protection ? programmable soft - start and voltage tracking ? frequency synchronization to external clock ? thermal shutdown ? operating ambient temperatur e up to 85c ? inrush current protection ? adjustable s oft start and sequencing ? cycle by cycle s hort circuit protection ? under - voltage and over - voltage power good ? pin compatible with we171040302 & we171060302 ? complies with en55022 class b radiated emissions standard v i n v o u t e n a b l e s s / t r i n t s s r t / c l k r r t c i n c o u t r s e t v a d j a g n d p g n d v i n v o u t p g v s e n s e + 2 7 2 8 6 7 4 3 6 3 5
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 2 / 29 package vin 30 vin 31 vin 32 agnd 33 agnd 34 vsense+ 36 vadj/fb 35 ccomp 2 comp 3 rt/clk 4 intrrt 5 ss/tr 6 intss 7 vout 8 v out 9 v out 10 12 v out 13 v out 14 vout 15 nc 16 nc 17 sw 18 sw 28 enable 27 pg 26 boot 25 sw 24 sw 23 sw 22 sw 21 sw 20 sw 37 gnd 38 v out 39 sw rcomp 1 v out 11 19 sw 29 uvlo
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 3 / 29 pin description symbol pin type description v in 30,31,32 power input voltage. place input capacitors as close as possible v out 8,9,10,11, 12,13,14,38 power output voltage. place output capacitors as close as possible. for thermal performance use copper plane(s) at these pins. agnd 5,7,33,34 supply analog ground for internal circuitry. connect to p ower g round p gnd 37 power power ground for the internal switching circuitry. connect to copper plane(s) with thermal vias for thermal performance. v sense + 3 6 input connect to positive terminal of the output capacitor. an internal resistor of 1430 ? is sense+ and v adj . t his is the upper resistor of the feedback voltage divider . v adj 35 input a resistor (r set ) from v adj to agnd is needed to select the output voltage. this is the lower resistor of the feedback voltage divider. rt/clk 4 input an external resistor from rt/clk to agnd adjusts the switching frequency of the device . intr rt 5 analog internal resistor which defines the default switching frequency . r comp 1 analog internal resistor of the compensation network . must be connected to agnd . optional symbol pin type description uvlo 29 input an internal u nder - voltage lock out resistor of 34 k? auxiliary symbol pin type description comp 3 output output of the error amplifier. if an external compensation is used, pin 1 must be left open . c comp 2 analog internal capacitor of the compensation network . do not connect. boot 26 supply internal bootstrap pin for the high side mosfet. switch 17,18,19,20 ,21,22,23, 24,25 ,39 power internal switch node. do not connect these pins . nc 15,16 not connected to internal circuitry.
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 4 / 29 o r dering information order code part description specifications package packaging unit 1710 4 0302 wpmd b 1 4 00362q 4 a / 14 . 5 w version bqfn - 39 tape and reel with 250 units pin compatible family members order code part description specifications package packaging unit 1710 2 0302 wpmdb 1 2 00362q 2 a / 7 . 2 w version bqfn - 39 tape and reel with 250 units 171060302 wpmdb 1600362q 6a / 21.6w version bqfn - 39 tape and reel with 250 units package specifications weight flammability mtbf 0.85g meets ul 94 v - o 3 2 . 8 mhrs, bellcore tr - 332, 50% stress, t a =40c, ground benign sales information sales contacts wrth elektronik eisos gmbh & co. kg emc & inductive solutions max - eyth - str. 1 74638 waldenburg germany tel. +49 (0) 7942 945 0 www.we - online.com powermodules@we - online.com
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 5 / 29 absolute maximum ratings caution: exceeding the listed absolute maximum ratings may affect the device negatively and may cause permanent damage. symbol parameter limits unit min (1) max ( 1 ) v in input voltage - 0.3 7 v v out output voltage - 0.6 v in v v adj feedback voltage - 0.3 3 v uvlo under - voltage lockout pin voltage - 0.3 3.3 v en enable pin voltage - 0.3 7 v enable source current - 100 a rt/clk rt/clk pin voltage - 0.3 6 v rt/clk source current - 100 a ss/tr ss/tr pin voltage - 0.3 3 v ss/tr pin sink current - 100 a pgood power good pin voltage - 0.3 7 v power good sink current - 10 ma comp output of the error amplifier - 0.3 3 v comp sink current - 100 a intss internal soft start capacitor - 0.3 3 v intrrt internal resistor for the initial switching frequency - 0.3 6 v r comp resistor of the compensation network - 0.3 3 v c comp capacitor of the compensation network - 0.3 3 v v sense+ sense for the output voltage. - 0.3 v out v v sw switch node voltage - 0.6 7 v sw 10ns transient - 2 7 v boot internal supply for the high mosfet driver - v sw +8v v t storage storage temperature - 65 150 c t solr peak case/leads temperature during reflow soldering, max. 30sec. (jedec j - std020) maximum three cycles! - 2455 c mechanical shock: mi l - std - 883d, method 2002.2, 1ms, ? sine, mounted - 1500 g mechanical vibration: mil - std - 883d, method 2007.2, 20 - 2000hz - 20 g
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 6 / 29 operating conditions operating conditions are conditions under which operation of the device is intended to be functional. all values are referenced to gnd. min and max limits are valid for the recommended ambient temperature range of - 40c to 85c . typical values represents statistically the utmost probability at following conditions: v in = 3.3v, v out = 1.8v, i out = 2a, c in1 = 47f ceramic, c in2 = 220f poly - tantalum, c out1 = 47 ceramic, c out2 = 100f poly - tantalum unless otherwise noted. symbol parameter min ( 1 ) typ ( 2 ) max ( 1 ) unit v in input voltage 2.95 - 6 v v out output voltage (depending on input voltage and switching frequency) 0.8 - 3.6 v t a ambient temperature range - 40 - 85 (3) c t jop j unction temperature range - 40 - 125 c thermal specifications symbol parameter typ (2) unit ? ja junctio n - to - ambient thermal resistance (4) 12 c/w jt junction - to - top (5) 2.2 c/w jb junction - to - board (6) 9.7 c/w t sd thermal shutdown , rising 175 c thermal shutdown hysteresis , falling 15 c
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 7 / 29 electrical specifications min and max limits are valid for the recommended ambient temperature range of - 40c to 85c . typical values represents statistically the utmost probability at following conditions: v in = 3.3v, v out = 1.8v, i out = 2a, c in1 = 47f ceramic, c in2 = 220f poly - tantalum, c out 1 = 47 ceramic, c out2 = 100f poly - tantalum unless otherwise noted. symbol parameter test conditions min ( 1 ) typ ( 2 ) max ( 1 ) unit output current i o cp output current protection - 7 - a accuracy v ref internal accuracy t a = 25c, i out = 0a with internal feedback resistor - - 1 (7) % temperature variation - 40ct a 85c, i out = 0a - 0.3 - % v out line regulation over v in range, t a = 25c, i out = 0a - 0.1 - % load regulation over i out range, t a = 25c - 0.1 - % total output voltage variation - - 1.5 % output voltage ripple 10f ceramic, 20mhz bw (8) - 9 - mv pp switching frequency f sw switching frequency using rt mode 500 - 2000 khz rt/clk pin open 400 500 600 khz f clk synchronization clock frequency range using clk mode 500 - 2000 khz minimum clk pulse width 75 - - ns v clk - h rt/clk high threshold relative to agnd 2.2 - 3.3 v v clk - l rt/clk low threshold - 0.3 - 0.4 v f clk rt/clk to switch node delay - 90 - ns pll lock - in - time - 14 - s enable and under - voltage lockout v uvlo v in under - voltage threshold v in increasing, uvlo pin connected to agnd - 3.05 3.135 v v in decreasing, uvlo pin connected to agnd 2.5 2.75 - v v enable enable threshold trip point enable logic high voltage - 1.25 - v enable logic low voltage - 0.3 - 1.0 v power good pg power good threshold v out rising, v out good - 93 - % v out rising, v out fault - 107 - % v out falling, v out good - 105 - % v out falling, v out fault - 91 - % power good low voltage i pg = 0.33ma - - 0.3 v
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 8 / 29 symbol parameter test conditions min ( 1 ) typ ( 2 ) max ( 1 ) unit efficiency in = 5v i out = 1a v out = 3.3v, f sw = 1 .0 mhz - 95 - % v out = 2.5v, f sw = 1 .0 mhz - 93 - % v out = 1.8v, f sw = 1 .0 mhz - 91 - % v out = 1.5v, f sw = 1.0mhz - 89 - % v out = 1.2v, f sw = 750khz - 97 - % v out = 1.0v, f sw = 650khz - 85 - % v out = 0.8v, f sw = 650khz - 84 - % v in = 3.3v i out = 1a v out = 1.8v, f sw = 1.0mhz - 90 - % v out = 1.5v, f sw = 1.0mhz - 88 - % v out = 1.2v, f sw = 750khz - 87 - % v out = 1.0v, f sw = 650khz - 84 - % v out = 0.8v, f sw = 650khz - 82 - % input and output capacitors c in external input capacitor ceramic 47 (9) - - f non ceramic - 220 (9) - f c out external output cpacitor ceramic 47 (10) 150 650 (11) f non ceramic - 100 (10) 2 000 (11) f output capacitor esr - - 25 m? transient response t tr transient response recovery time 1a/s load step from 1 . 0 a to 3 a - 80 - s t tr v out over/undershoot 1a/s load step from 1.0 a to 3 a - 90 - mv input standby current i q input quiescent current enable logic low - 70 100 a
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 9 / 29 notes (1) min and max limits are 100% production tested at 25c. limits over the operating temperature range are guaranteed through correlation using statistical quality control (sqc) methods. (2) typical numbers are valid at 25c ambient temperature and represent statistically the utmost probability assuming the gaussian distribution. (3) depending on heat sink design, number of pcb layers, copper thickness and air flow. (4) measured on a 100 x 100mm two layer board, with 35m (1 ounce) copper, no air flow (5) the junction - to - top characterization parameter, jt , estimates the junction temperature, t j , of a device in a real system, using a procedure described in jesd51 - 2a (sections 6 and 7). t j = jt * p dis + t t ; where p dis is the power dissipated in the device and t t is the temperature of the top of the device. (6) the junction - to - board characterization parameter, jb , estimates the junction temperature, t j , of a device in a real system, using a procedure described in jesd51 - 2a (sections 6 and 7). t j = jb * p dis + t b ; where p dis is the power dissipated in the device and t b is the temperature of the board 1mm from the device. (7) the stated limit of the set - point voltage tolerance incl udes the tolerance of both the internal voltage reference and the internal adjustment resistor. the overall output voltage tolerance is affected by the tolerance of the external rset resistor. (8) the industry standard for comparison of the output voltage ripp le between switching regulators or modules requires a 10f ceramic (sometimes additional 1f ceramic in parallel) at the point of load where the voltage measurement is done using an oscilloscope with its probe and probe jack for low voltage/high frequency (low impedance) measurement. the oscilloscopes bandwidth is limited at 20mhz. (9) a minimum of 47f of ceramic capacitance is required across the input for proper operation. locate the capacitor directly at v in of the device. an additional 220f of bulk capaci tance is recommended. (10) the amount of required output capacitance varies depending on the output voltage. the amount of required capacitance must include at least 47f of ceramic capacitance. locate the capacitance close to the device. adding additional capa citance close to the load improves the response of the regulator to load transients. (11) when using both ceramic and non - ceramic output capacitance, the combined maximum must not exceed 1200f.
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 10 / 29 typical performance curves if not otherwise specified, the following conditions apply: v in = 3.3v - 5 v; c in = 2 x 47 f x7r ceramic; c out = 2x 47f x7r ceramic, t amb = 25c. radiated emissions en55022 (cispr - 22) class b compliant measured on module with pcb and without external filters at 3m antenna distance measured on module with pcb and without external filters at 3m antenna distance 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 3 0 1 0 0 1 0 0 0 f r e q u e n c y [ m h z ] r a d i a t e d e m i s s i o n s d b [ v / m ] r a d i a t e d e m i s s i o n s v i n = 3 . 3 v , v o u t = 1 . 8 v , f s w = 1 m h z , i l o a d = 4 a e n 5 5 0 2 2 c l a s s b h o r i z o n t a l v e r t i c a l 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 3 0 1 0 0 1 0 0 0 f r e q u e n c y [ m h z ] r a d i a t e d e m i s s i o n s d b [ v / m ] r a d i a t e d e m i s s i o n s v i n = 5 v , v o u t = 1 . 8 v , f s w = 1 m h z , i l o a d = 4 a e n 5 5 0 2 2 c l a s s b h o r i z o n t a l v e r t i c a l
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 11 / 29 input voltage 5v
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 12 / 29 input voltage 3.3v
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 13 / 29 block diagram circuit description the magi3c power module 171020302 is based on a synchronous step down regulator with integrated mosfet s and a power inductor. the control scheme is based on a current mode (cm) regulation loop. the v out of the regulator is divided with the feedback resistor network of internal 1430? and external r set and fed into the v adj pin. the error amplifier compares this signal with the internal 0.8 03 v referenc e. the error signal is amplified and controls the on - time of a fixed frequency pulse with generator. this signal drives the power mosfets. the current mode architecture features a constant frequency during load steps. only the on - time is modulated. it is internally compensated and stable with low esr output capacitors and requires no external compensation network. this architecture supports fast transient response and very small output ripple values of 10ths of millivolts are achieved. i n t s s r t / c l k v a d j p g v s e n s e + 1 h c i n c o u t v i n v o u t 1 4 3 0 ? r s e t 4 8 . 7 k 3 4 k e n a b l e s s / t r s w c b o o t 1 0 0 n u v l o v o u t p g n d c c o m p c o n t r o l l e r / p o w e r c o n t r o l / p r o t e c t i o n c i r c u i t r y b o o t r c o m p i n t r r t a g n d c o m p 7 6 5 4 3 2 1 3 5 3 6 2 6 2 8 2 9 2 7 r e f
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 14 / 29 design flow the next 10 simple steps will show how to select the external components to design your power application. essential steps 1. set output voltage 2. set operating frequency 3. select input capacitor 4. select output capacitor optional steps 5. select soft start capacitor 6. select under - voltage lockout divider 7. enable / disable 8. voltage tracking 9. synchronization to an external clock 10. power good step 1 s etting the output voltage (v out ) the output voltage is selected with a resistor divider across vadj pin and agnd. the upper resistor of 1430 ? of the feedback voltage resistor divider is internal to the module. the output voltage adjustment range is from 0.8v to 3.6v. ? ??? = 0 . 8v ? 1430? v out ? 0 . 8v (?) (1) v out 3.3v 3.0v 2.5v 1.8v 1.5v 1.2v 1.0v 0.8v r set (e96) 453? 523? 665? 1130? 1620? 2870? 5620? v i n v o u t e n a b l e s s / t r i n t s s r t / c l k r r t c i n c o u t r s e t v a d j a g n d p g n d v i n v o u t p g v s e n s e + 2 7 2 8 6 7 4 3 6 3 5 1 2 3 4 5 6 7 8 9 1 0 r u v l o 1 r u v l o 2 c s s
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 15 / 29 step 2 setting the operating frequency (f sw ) the switching frequency must be selected according to input voltage, output voltage and load current for the best performance in loop regulation and transient response. note: r rt open (f sw = 500 khz) is only allowed under specific conditions per below table! v in = 5v v in = 3.3v operating frequency [khz] i out = 0 to 3.5a i out > 3.5a i out = 0 to 4a v out range [v] v out range [v] v out range [v] r rt [k?]
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 16 / 29 step 3 select input capacitor (c in ) the 171020302 magi3c power module contains an 100nf internal input capacitor for good emi performance . additional input capacitance is required external to the magi 3 c power module to handle the input ripple current of the application. therefore an external input capacitance placed directly at the v in pin is required to handle the input ripple current of the application. the input capacitor can be several capacitors in parallel. input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. input ripple current rating is dictated by the equati on: ? ? ????? 1 2 ? ? ??? ? ? 1 ? ? (2) where ? ? ??? ? ?? as a point of reference, the worst case ripple current will occur when the module is presented with full load current and whe n v in = 2 x v out . recommended minimum input capacitance is 4.4f x7r ceramic with a voltage rating at least 25% hig her than the maximum applied input voltage for the application. it is also recommended that attention be paid to the voltage and temperature deratings of the capacitor selected. it should be noted that ripple current rating of ceramic capacitors may be mis sing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating. if the system design requires a certain minimum value of peak - to - peak input ripple voltage ( v in ) be maintained then the following equation may be u sed: ? ?? ? ??? ? ? ? ( 1 ? ? ) ? ?? ??? ? ? ? ?? (3) where ? ? ??? ? ?? ccm = continuous conduction mode additional bulk capacitance with higher esr may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines.
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 17 / 29 step 4 select output capacitor (c out ) none of the required output capacitance is integrated within the module. at a minimum, the output capacitor must meet the worst case rms current rating of 0 . 5 ? ? ???? , as calculated in equation ( 4 ). ? ?? ?? = ? ??? ? ( ? ?? ? ? ??? ) 1 ? ? ? ?? ? ? ?? (4) beyond that, additional capacitance will reduce output ripple so long as the esr is low enough to permit it. a minimum value of 10f is generally re quired. please consider the derating of the nominal capacitance value dependent on the dc voltage applied across it. experimentation will be required if attempting to operate with a minimum value. low esr capacitors, such as ceramic and polymer electrolyti c capacitors are recommended. ? ??? ? ? ??? ? ? ??? ? ? ? ? ?? 4 ? ? ??? ? ( ? ?? ? ? ??? ) ? ? ? ??? (5) where i out is the load step in a, and v out is the maximum allowed voltage drop at the output voltage. the esr of the output capacitor affects the output voltage ripple. high esr will result in larger v out peak - to - peak ripple voltage. furthermore, high output voltage ripple caused by excessive esr can trigger the over - voltage protection monitored at the v sense+ pin. the esr should be chos en to satisfy the maximum desired v out peak - to - peak ripple voltage and to avoid over - voltage protection during normal operation. the following equations can be used: ?? ? ??? ? ??? ?????? ? ? ?????? (6) where ? ??? ?????? is the maximal wanted output ripple generated by esr and ? ? ?????? is the inductor ripple current calculated in equation (4).
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 18 / 29 step 5 select soft - start capacitor (c ss ) connecting the intss pin to agnd and leaving ss/tr pin open enables the internal soft start capacitor with a soft - start interval of approximately 1.1 ms. adding additional capacitance between the ss/tr pin and agnd increases the soft - start time according to the table below. c ss [nf] open 2.2 4.7 10 15 22 25 soft start [ms] 1.1 1.9 2.8 4.6 6.4 8.8 9.8 step 6 select under - voltage lockout divider pin 29 connected to analog ground this connects the internal under - voltage lockout resistor divider. the enable rising threshold is typ. 1.25v. the enable falling threshold is at 1v max. use at least 10% safety tolerance. for 3.3v input voltage use a rising threshold of below 3v which is achievable with pin 29 left open. an external under - voltage lockout resistor will set the rising threshold below 3v. v in(uvlo) rising threshold typ. [v] 3.14v hysteresis [mv] 300 v i n 4 8 . 7 k ? 3 4 k ? e n a b l e 2 9 2 8 s h u t d o w n l o g i c a g n d s s / t r i n t s s c s s 7 6 a g n d
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 19 / 29 pin 29 connected to agnd with additional resistor to adjust under - voltage lockout . v in(uvlo) rising threshold typ. [v] 3.25 3,5 3,75 4,0 4,25 4,5 4,75 r uvlo [k?] pin 29 open with additional resistor to adjust under - voltage lockout for lower values. v in(uvlo) rising threshold typ. [v] 3.0 2.75 2.5 2.25 r uvlo [k?] step 7 enable apply a voltage 1v to the enable pin to disable the device. left open or set to 1.5v will enable the device. when disabeling use short leads to connect to agnd of the module. if not applicable use a transistor as below. the en pin provides electrical o n/off control of the device. once the en pin voltage exceeds the threshold voltage, the device starts operation. if the en pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low quiescen t current state. v i n 4 8 . 7 k ? 3 4 k ? e n a b l e 2 9 2 8 s h u t d o w n l o g i c r u v l o a g n d v i n 4 8 . 7 k ? n o t u s e d e n a b l e 2 9 2 8 s h u t d o w n l o g i c r u v l o a g n d e n a b l e 2 8 a g n d
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 20 / 29 step 8 voltage tracking many of the common power supply sequencing methods can be implemented using the ss/tr, enable and p g pins. the sequential voltage tracking is illustrated below using two devices. the pg pin of the first device is coupled to the enable pin of the second device which enables the second power supply once the pri mary supply reaches regulation. simultaneous tracking simultaneous power supply sequencing can be implemented by connecting the resistor network of r 1 and r 2 as shown below to the output of the power supply that needs to be tracked or to another voltage reference source . ? 1 = ? ??? 2 ? 12 . 6 0 . 803 (k?) (7) ? 2 = 0 . 803 ? ? 1 ? ??? 2 ? 0 . 803 (k ?) (8) e n a b l e s s / t r i n t s s p g e n a b l e s s / t r i n t s s p g 2 8 2 8 2 7 2 7 7 7 6 6 s s / t r c s s c s s a g n d a g n d e n a b l e s s / t r i n t s s v o u t 1 e n a b l e s s / t r i n t s s v o u t 2 r 1 r 2 2 8 2 8 6 6 7 7 c s s c s s a g n d a g n d
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 21 / 29 step 9 synchronizing to an external clock an internal phase locked loop (pll) has been implemented to allow synchronization between 500 khz and 2 mhz, and to easily switch from rt mode to clk mode. to implement the synchronization feature, connect a square wave clock signal to the rt/clk pin with a minimum pulse width of 75 ns. the maximum clock pulse width must be calculated using e quation 9 . the clock signal amplitude must transition lower than 0.4 v and higher than 2.2 v. the start of the switching cycle is synchronized to the falling edge of rt/clk pin. applications requiring both rt mode and clk mode, configure the device as shown in figur e 1 . before the external clock is present, the device works in rt mode and the switching frequency is set by the rt resistor (r rt ). when the external clock is present, the clk mode overrides the rt mode. the device switches from rt mode to clk mode and the rt/clk pin becomes high impedance as the pll starts to lock onto the frequency of the external clock. the device will lock to the external clock frequency approximately 15 s after a valid clock signal is present. it is not recommended to switch from clk mode back to rt mode because the internal switching frequency drops to a lower frequency before returning to the switching frequency set by the rt resistor. maximum clock pulse width = 0 . 75 ? ( 1 ? v out v inmin ) f sw (9) figure 1 step 10 power good the p g pin is an open drain output. once the voltage on the sense+ pin is between 93% and 107% of the nominal v alue , the pg pin pull - down is released and the pin floats. the recommended pull - up r esistor value is between 10 k ? and 100 k ? to a voltage source that is 6 v or less. the pg pin is in a defined state once v in is greater than 1.2 v, but with reduced current sinking capability. the pg pin achieves full current sinking capability once the v i n pin is above 2.95v. the p g pin is pulled low when the voltage on sense+ is lower than 91% or greater than 109% of the nominal set voltage. also, the p ower good pin is pulled low if the input uvlo or thermal shutdown is asserted, or if the enable pin is pulled low. r t / c l k r r t 1 k ? 4 7 0 p f e x t e r n a l c l o c k g e n e r a t o r 7 a g n d p g 1 0 k ? v c c = v i n o r o t h e r s u p p l y v o l t a g e b e l o w 6 v 2 7 v c c a g n d
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 22 / 29 protective features over temperature protection (otp) for protection against load faults, the magi3c power module incorporates cycle - by - cycle current limiting. during an overcurrent condition the output current is limited and the output voltage is reduced. as the output voltage drops more than 9% below the se t point, the pg signal is pulled low. if the output voltage drops more than 25%, the switching frequency is reduced to reduce power dissipation within the device. when the overcurrent condition is removed, the output voltage returns to the established volt age. over current protection (ocp) the junction temperature of the magi3c power module should not be allowed to exceed its maximum ratings. thermal protection is implemented by an internal thermal shutdown circuit which activates at 175c (typ) causing the device to enter a low power standby state. in this state the main mosfet remains off causing v out to fall, and additionally the c ss capacitor is discharged to ground. thermal protection helps prevent catastrophic failures for accidental device overhea ting. when the junction temperature falls back below 160 the ss pin is released, v out rises smoothly, and normal operation resumes. applications requiring maximum output current especially those at high input voltage may require additional derating at ele vated temperatures. short circuit protection (scp) the short circuit protection is realized via the cycle by cycle current limiting. the short circuit protection is indefi - nite with a recovery at the following switching cycle if the short circuit is removed.
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 23 / 29 typical schematic input output c in2 c in1 r rt r set c out1 c out2 5v 3.3v 220 47f x5r 174k? 459? 174k? 673? 348k? 1150? 348k? 1650? 715k? 2870? 715k? 5830? 1200k? 348k? 1150? 348k? 1650? 715k? 2870? 715k? 5830? 1200k? in2 and c out2 100f are polymer tantalum types. v i n v o u t e n a b l e s s / t r i n t s s r t / c l k r r t c i n 2 c o u t 1 r s e t v a d j a g n d p g n d v i n v o u t p g c i n 1 c o u t 2 6 2 7 2 8 7 4 3 5
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 24 / 29 handling recommendations 1. the power module is classified as msl3 (jedec moisture sensitivity level 3) and requires special handling due to moisture sensitivity (jedec j - std033). 2. the parts are delivered in a sealed bag (moisture barrier bags = mbb) and should be processed within one year. 3. when opening the moisture barrier bag check the humidity indicator card (hic) for color status. bake parts prior to soldering in case indicator color has changed according to the notes on the card. 4. parts must be processed after 168 hour (7 days) of floor life. once this time has been exceeded, bake parts prior to soldering per jedec j - std033 recommendation. solder profile 1. only pb - free assembly is recommend ed according to jedec j - std020. 2. measure the peak reflow temperature of the magi3c power module in the middle of the top view. 3. ensure that the peak reflow temperature does not exceed 245 c 5c as per jedec j - std020. 4. the reflow time pe riod during peak temperature of 245c 5c must not exceed 30 seconds. 5. reflow time above liquidus (217 c) must not exceed 90 seconds. 6. maximum ramp up is rate 3c per second. 7. maximum ramp down rate is 3c p er second. 8. reflow time from room (25c) to peak mus t not exceed 8 minutes as per jedec j - std020. 9. maximum num bers of reflow cycles is three. 10. for minimum risk, solder the module in the last refl ow cycle of the pcb production. 11. for soldering process please consider lead material copper (cu) and lead finish tin (sn). 12. for solder paste use a standard sac alloy suc h as sac 305, type 3 or higher. 13. below profile is v alid for convection reflow only. 14. other soldering methods (e.g.vapor phase) are not verified and have to be validated by the custo mer on his own risk . t e m p e r a t u r e [ c ] t i m e [ s e c ] 1 5 0 1 8 0 2 1 7 m a x 2 5 0 m a x 1 2 0 s e c m i n 6 0 s e c m a x 9 0 s e c m i n 3 0 s e c m a x 1 0 - 3 0 s e c 2 4 5 c r a m p u p r a t e m a x 3 c / s e c r a m p d o w n r a t e m a x 3 c / s e c m a x 3 s o l d e r c y c l e s ! p r e h e a t l i q u i d u s p e a k
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 25 / 29 physical dimensions bottom view all dimensions in mm
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 26 / 29 example stencil design stencil thickness 0.125mm
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 27 / 29 document history revision date description comment 0 . 1 31.03.2015 preliminary version
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 28 / 29 cautions and warnings the following conditions apply to all goods within the product series of magi3c of wrth elektronik eisos gmbh & co. kg: general: all recommendations according to the general technical specifications of the data - sheet have to be complied with. the usage and operation of the product within ambient conditions which probably alloy or harm the component surface has to be avoided. the responsibility for the applicability of customer specific products and use in a particular customer design is always within the authority of the customer. all technical specifications for standard products do also apply for customer specific product s. res idual washing varnish agent that is used during the production to clean the application might change the characteristics of the body, pins or termination. the washing varnish agent could have a negative effect on the long term function of the product. dire ct mechanical impact to the product shall be prevented as the material of the body, pins or termination could flake or in the worst case it could break. as these devices are sensitive to electrostatic discharge customer shall follow proper ic handling proc edures. customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety - related requirements concerning its products, and any use of wrth elektronik eisos gmbh & co. kg components in its applications, n otwithstanding any applications - related information or support that may be provided by wrth elektronik eisos gmbh & co. kg. customer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerou s consequences of failures, monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions. customer will fully indemnify wrth elektronik eisos and its representatives against any dama ges arising out of the use of any wrth elektronik eisos gmbh & co. kg components in safety - critical applications. product specific: follow all instructions mentioned in the datasheet, especially: ? the solder profile has to comply with the technical reflow or wave soldering specification, otherwise this will void the warranty. ? all products are supposed to be used before the end of the period of 12 months based on the product date - code. ? violation of the technical product specifications such as exceeding the absolute maximum ratings will void the warranty. ? it is also recommended to return the body to the original moisture proof bag and reseal the moisture proof bag again. ? esd prevention methods need to be followed for manual handling and processing by machine ry.
wpmdb1 4 00 362q / 1710 4 0302 magi 3 c power module vdrm C variable step down regulator module we - online.com wrth elektronik eisos gmbh & co. kg C preliminary data sheet rev 0 . 1 ? mai 2015 29 / 29 important notes the following conditions apply to all goods within the product range of wrth elektronik eisos gmbh & co. kg: 1. general customer responsibility some goods within the product range of wrth elektronik eisos gmbh & co. kg contain statements regarding general suitability for certain application areas. these statements about suitability are based on our knowledge and experience of typical requirements concerning the areas, serve as general guidance and cannot be estim ated as binding statements about the suitability for a customer application. the responsibility for the applicability and use in a particular customer design is always solely within the authority of the customer. due to this fact it is up to the customer t o evaluate, where appropriate to investigate and decide whether the device with the specific product characteristics described in the product specification is valid and suitable for the respective customer application or not. accordingly, the customer is c autioned to verify that the datasheet is current before placing orders. 2. customer responsibility related to specific, in particular safety - relevant applications it has to be clearly pointed out that the possibility of a malfunction of electronic compone nts or failure before the end of the usual lifetime cannot be completely eliminated in the current state of the art, even if the products are operated within the range of the specifications. in certain customer applications requiring a very high level of s afety and especially in customer applications in which the malfunction or failure of an electronic component could endanger human life or health it must be ensured by most advanced technological aid of suitable design of the customer application that no in jury or damage is caused to third parties in the event of malfunction or failure of an electronic component. 3. best care and attention any product - specific notes, warnings and cautions must be strictly observed. 4. customer support for product specifica tions some products within the product range may contain substances which are subject to restrictions in certain jurisdictions in order to serve specific technical requirements. necessary information is available on request. in this case the field sales en gineer or the internal sales person in charge should be contacted who will be happy to support in this matter. 5. product r&d due to constant product improvement product specifications may change from time to time. as a standard reporting procedure of the product change notification (pcn) according to the jedec - standard we inform about minor and major changes. in case of further queries regarding the pcn, the field sales engineer or the internal sales person in charge should be contacted. the basic respons ibility of the customer as per section 1 and 2 remains unaffected. 6. product life cycle due to technical progress and economical evaluation we also reserve the right to discontinue production and delivery of products. as a standard reporting procedure of the product termination notification (ptn) according to the jedec - standard we will inform at an early stage about inevitable product discontinuance. according to this we cannot guarantee that all products within our product range will always be available. therefore it needs to be verified with the field sales engineer or the internal sales person in charge about the current product availability expectancy before or when the product for application design - in disposal is considered. the approach named above does not apply in the case of individual agreements deviating from the foregoing for customer - specific products. 7. property rights all the rights for contractual products produced by wrth elektronik eisos gmbh & co. kg on the basis of ideas, development contracts as well as models or templates that are subject to copyright, patent or commercial protection supplied to the customer will remain with wrth elektronik eisos gmbh & co. kg. wrth elektronik eisos gmbh & co. kg does not warrant or represent that any license, either expressed or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, application, or process in which wrth elektronik eisos gmbh & co. kg components or services are used. 8. general terms and conditions unless otherwise agreed in individual contracts, all orders are subject to the current version of the general terms and conditions of wrth elektronik eisos group, last version available at www.we - onlin e.com.

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